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24.4 Register Map
The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
Name
VCMP_CTRL
VCMP_INPUTSEL
VCMP_STATUS
VCMP_IEN
VCMP_IF
VCMP_IFS
VCMP_IFC
Type
RW
RW
R
RW
R
W1
W1
Description
Control Register
Input Selection Register
Status Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
24.5 Register Description
24.5.1 VCMP_CTRL - Control Register
Offset
0x000
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
30
HALFBIAS
1
RW
Half Bias Current
Set this bit to 1 to halve the bias current. Table 24.1 (p. 334) .
29:28
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
27:24
BIASPROG
0x7
RW
VCMP Bias Programming Value
These bits control the bias current level. Table 24.1 (p. 334) .
23:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17
IFALL
0
RW
Falling Edge Interrupt Sense
Set this bit to 1 to set the EDGE interrupt flag on falling edges of comparator output.
16
IRISE
0
RW
Rising Edge Interrupt Sense
Set this bit to 1 to set the EDGE interrupt flag on rising edges of comparator output.
15:11
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
10:8
WARMTIME
0x0
RW
Warm-Up Time
Set warm-up time
Value
0
1
2
3
4
5
6
Mode
4CYCLES
8CYCLES
16CYCLES
32CYCLES
64CYCLES
128CYCLES
256CYCLES
Description
4 HFPERCLK cycles
8 HFPERCLK cycles
16 HFPERCLK cycles
32 HFPERCLK cycles
64 HFPERCLK cycles
128 HFPERCLK cycles
256 HFPERCLK cycles
2011-04-12 - d0001_Rev1.10
337
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